1. Field of the Invention
The present invention relates to an integrated circuit having an electrostatic discharge protection device that is triggered by a circuit that provides hysteresis.
2. Description of the Prior Art
The protection of integrated circuits (ICs) from electrostatic discharge (ESD) has received considerable design attention, especially as circuit geometries advance to smaller (i.e., sub-micron) dimensions. There are various techniques for protecting input, output, and power supply bondpads on the ICs from ESD damage, which damage may occur during manufacture of the IC chip, or more frequently after the chip is packaged. In the latter case, the ESD voltages are transmitted to the chip bondpads via package terminals, which may be subjected to the ESD voltages during handling, shipment, or subsequent use, for example. One form of ESD protection utilizes voltage clamping diodes to protect the IC circuitry connected to the bondpads, while another technique uses input or output resistors to reduce the ESD voltages transmitted to the IC from the bondpads. In still another form of ESD protection, a transistor is used to clamp the operating voltage on a bondpad to a safe level. It is also known to use a four-layer device (e.g. a thyristor) to introduce hysteresis into the protective circuitry. In that manner, a slightly excessive power supply voltage may be present, as for testing purposes, without triggering the protective circuitry. However, in many IC fabrication processes, a four-layer device is not readily implemented.
One form of transistor protection circuitry is shown in FIG. 1, wherein the protection circuit 10 clamps the voltage between the V.sub.DD conductor 12 and the V.sub.SS conductor 13 to a safe level when potentially damaging ESD voltage levels are present between V.sub.DD power supply bondpad 11 and V.sub.SS power supply bondpad 14. For this purpose, the protection circuit 10 comprises a voltage clamping PNP transistor 15 having its emitter and collector connected to the V.sub.DD and V.sub.SS power supply conductors, respectively. The base of transistor 15 is connected to a trigger circuit comprising resistors 16 and 17, and control transistor 18. The gate of the n-channel control transistor 18 is in turn connected to a voltage divider comprising a stack of p-channel transistors 19-25 and a resistor 26. In normal operation, the voltage drop across each of the transistors 19-27 is about 1 volt, and so the voltage at divider node 27 remains below 1 volt when normal power supply voltages (e.g., V.sub.DD =5 volts and V.sub.SS =0 volts) are present. Therefore, the voltage on the gate of transistor 18 is below the conduction threshold, being about 1 volt for an IC implemented in a typical CMOS (complementary metal oxide silicon) technology. This non-conduction of control transistor 18 causes control node 28 to remain at a high voltage level, approximately V.sub.DD, SO that the base of protection transistor 15 is biased to a non-conducting state. Therefore, no significant current conduction occurs through the protection transistor 15 in normal operation.
However, when excessively high voltages (as may be due to ESD) are present between the power supply conductors 12 and 13, the voltage at divider node 27 increases beyond the threshold of control transistor 18, allowing it to conduct. This conduction pulls the control node 28 low, so that the voltage on the base of transistor 15 is biased so as to allow transistor 15 to conduct. Therefore, a significant current flow through transistor 15 helps to dissipate the ESD electrical charge, preventing an excessive voltage from appearing between the power supply conductors 12 and 13. This voltage-clamping action protects other circuitry (not shown) that is coupled either directly or indirectly to the power supply conductors 12 and 13. The clamping voltage at which the circuitry 10 conducts is determined to a significant degree by the number of the voltage-divider transistors, being 7 in the illustrative case (e.g., transistors 19-25). A larger number allows for conduction at a higher voltage; for example, an additional voltage-divider transistor (for a total of 8) has been used to allow for testing of an integrated circuit at higher than normal power supply voltages (e.g., V.sub.DD =7 volts) without triggering the protective circuit 10. The size and length-to-width ratio of the voltage-divider transistors, as well as their construction, also influences the voltage drop across each transistor, and hence the clamping voltage of the circuitry 10.
A problem has remained however in obtaining a protection circuit that provides a high degree of protection during an ESD event, while still preventing triggering of the protection circuit at slightly higher than normal voltages on the bondpads that are connected to the protection circuitry. Such higher than normal voltages may occur, for example, during testing of the integrated circuit; e.g., testing at 7 volts for an integrated circuit designed for nominal 5 volt operation. In still another case, it is desired to interface integrated circuits operating at 3 volts with external circuitry operating at higher levels (e.g., 5 volts). In that case, it is necessary to avoid triggering any ESD protection circuitry connected to the input bondpads of the 3 volt IC from the 5 volt high logic levels.